A semiconductor integrated circuit is equipped with a large number of circuit elements due to an improvement of degree of the integration of the semiconductor integrated circuit. In particular, the large-scale integrated circuit (LSI: Large Scale Integrated Circuit) is equipped with several hundred thousand or several million circuit elements. A functional test of the large-scale integrated circuit (hereinafter referred to as LSI) is effective in order to perform research, analysis and confirmation of the internal circuits.
A boundary scan test has been used as an operation test of the internal circuits in the LSI and a test of a board after mounting the LSI on a printed circuit board. A test method by the JTAG (Joint Test Action Group) of IEEE 1149.1 (IEEE: The Institute of Electrical and Electronic Engineers, Inc) standard is a representative example of the boundary scan test.
FIG. 14 is a block diagram of a scan test by the JTAG. FIG. 15 is a time chart of control signals in FIG. 14. As depicted by FIG. 14, a logic circuit 200 of the test target is configured of a plurality of flip-flop circuits 200-1˜200-M. These flip-flop circuits (hereinafter referred to as FF) 200-1˜200-M are connected in series (called to scan chain). And the FF is one type of cell, and has a shift register and a latch circuit, in general.
In the JTAG scan method, an exclusive path of the test is provided for the test logic circuit 200. Signal lines from the external device include TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock), TMS (Test Mode Select), and TRST (Test Reset). The TDI is a signal which serial inputs a command and data to the test logic circuit 200 (200-1˜200-M). The TDO is a signal which serial outputs data from the test logic circuit 200 (200-1˜200-M).
The TCK provides clock to the test logic circuit 200 (200-1˜200-M). The TMS is a signal for controlling the test operation. The TRST is a signal for asynchronously initializing a TAP (Test Access Port) controller 210 (as described later).
The TAP controller 210 is a state machine which performs to capture, to shift, and to update, as a major operation. The TAP controller 210 receives a start of a designation of a mode via the TMS signal line. And the TAP controller 210 sets a mode instruction from the TDI into an instruction register (not indicated by FIG. 14).
The TAP controller 210 supplies shift clocks “dack” and “dbck” as illustrated in FIG. 15 to each of the FF 200-1˜200-M. By the shift clocks “dack” and “dbck”, each of the FF 200-1˜200-M performs to fetch data into the shift register, to output the contents of the shift register, and to fix to the latch circuit.
The TAP controller 210 performs the scan test by supplying the shift clocks “dack” and “dbck” to the FF 200-1˜200-M, sequentially shifting the data to FF 200-2˜200-M of the next stage, and outputting the data from the TDO signal line.
On the other hand, as the test method of the semiconductor integrated circuit itself, a test device inputs a serial test pattern to the logic circuit which is configured of a multi-stage flip flop circuits, fetches the output of the logic circuit, and determines whether or not the output is the inputted test pattern. This method is effective as a test method whether or not the operation of each FF itself in the logic circuit is normal, prior to a shipment of the semiconductor integrated circuit.